Microsystems packaging involves the assembly and interconnection of microelectronics, microelectromechanical systems (MEMS), photonics, RF/wireless, fluidic, and other microscale devices into a system-level board or chip to form an integrated microsystems product. Microsystems packaging must satisfy more complex and diverse requirements than a strictly microelectronic package. In addition to the interconnection of electrical components, microsystems packaging requires the interconnection of actuators, sensors, and other devices. In addition, a microsystem package must provide for environmental protection, thermal management, mechanical support, power and signal distribution, testing, and connection with the outside world. Therefore, packaging often controls the microsystem's performance, cost, size, and reliability. Portable products, in particular, are driving the development of very dense packaging concepts comprising integrated electronic, optical, mechanical, chemical, and biological functions. A major roadblock in developing a highly miniaturized microsystem is the difficulty in integrating the different device technologies in a small volume. However, packaging concepts are evolving toward the full integration of a variety of functions into a complete system on a single chip.
As shown in FIG. 1, microelectronics packaging involves multiple levels of integration. A traditional circuit board 120 comprises integrated circuits (ICs) 122 and passives 124 that are individually packaged, attached to a printed wiring board (PWB) 126 and interconnected by external wiring lines (e.g., copper foil tracks) on the surface of the PWB 126. Single chip packages 132 and 136 typically comprise the electrical component, a bonding structure of the component to the package, and a means to attach the package to the PWB 126. For example, for surface mount assembly of a plastic package 132 the IC 122 can be encapsulated in a plastic 133 and wirebonded to a lead frame 134 that is solder-bonded to electrically conductive pads on the PWB 126. In a ceramic package 136 the IC 122 can be wirebonded to a ceramic chip carrier 137 that is bonded to the PWB 126 by a ball grid array, or the like. The ceramic package 136 can be hermetically sealed by a metal cap 138. In addition to active devices, the microelectronics package can also comprise discrete and/or integrated passive devices (IPDs) 124, such as resistors and capacitors, surface mounted in a hybrid fashion on the PWB 126. Power can also be brought into and signals taken out of the active devices by plated through-holes or vias 128.
With the PWB, the best miniaturization that can be achieved provides a footprint that is the sum-total of the single-chip packages, passives, and interconnection areas. Furthermore, the high frequency electrical performance of in-plane hybrid circuits can be degraded, as a result of transmission line effects and circuit parasitics, thus limiting such packages for RF applications. In addition, wirebonds or solder joints pose a major reliability concern in such hybrid packages.
At the next level of integration, a multichip module (MCM) 140 comprises bare chips 122 and passives 124 mounted directly to a common substrate/package structure that replaces the chip-level packaging of the traditional circuit board. The MCM substrate 146 can comprise a deposited metal/dielectric multilayer structure on a base layer, a thick-film or cofired multilayer ceramic, or an organic laminate multilayer structure. The MCM substrate 146 provides signal input/output connections for the chips, signal interconnection through conducting layers 148 sandwiched between the multilayer dielectric structure, thermal management, mechanical support, and environmental protection. The bare chips 122 can be placed close together and directly bonded to the substrate 146 by the use of flip chip or other direct chip attach technology. This saves the weight and volume of individual chip packaging, significantly reducing the footprint of the MCM 140. The MCM 140 can be hermetically sealed in ceramic or metal packages or encapsulated in plastic (not shown). The MCM 140 typically enables a higher packaging efficiency, better electrical performance, greater reliability, and lower cost than the traditional circuit board 120.
As an approach to building a more compact, three-dimensional (3D) package, integrated substrate technology 160 uses passives that are embedded (i.e., integral passives 168) as part of the fabrication of the multilayer substrate 166. Bare chips 122 can be assembled directly above the embedded passives 168, shortening interconnection distances and thereby further improving electrical performance and enabling higher packaging efficiency, lower assembly costs, and small size and weight. However, such integral substrates 166 require new designs, test systems, manufacturing processes, and materials and can therefore by more costly to develop and have a longer time-to-market than with PWB or MCM packages 120 or 140.
Fully 3D integration of components is being developed, as a result of the increasing demand for portability and miniaturization. Therefore, the longer-term goal of modern packaging is the system-on-chip (SOC) 180. Hybrid SOC packaging uses thinned silicon chips that are stacked on top of a bottom wafer of normal thickness and interconnected by vertical electrical connections. Therefore, the SOC package can provide a high level of vertical integration and interconnection, such that the package footprint is the size of the largest component. In addition, stacking and interchip wiring may provide improvements in performance and reliability. In particular, interconnect delays can be dramatically reduced by replacing long in-plane interconnects with through-wafer via interconnects.
There are several hybrid SOC packaging concepts being developed worldwide. One approach uses a modification of MCM packaging technology. In this stacked MCM approach, multiple physical layers are built-up, starting with a first physical layer comprising thinned dies mounted on a substrate carrier. The in-layer dies can be interconnected with several metal deposition and etching steps, using spin-on polymer with corresponding via formation. Additional physical layers are then built up from an insulating and planarizing polymer layer on the first physical layer. While providing many of the advantages of the MCM packaging in a stacked 3D package, handling thin dies can be challenging and parallel assembly of individual chips does not provide the efficiencies of wafer-level packaging. See Vendier et al., “Ultra Thin Electronics for Space Applications,” Proc. 2001 Electronic Components and Technology Conference (2001), which is incorporated by reference.
Another SOC concept uses flip-chip interconnection to build a chip-on-chip (COC) structure. With the COC structure, through-hole copper electrodes on the periphery of thinned silicon chips are connected to electroplated gold micro bumps on the underlying wafer by thermal compression flip-chip bonding. The narrow gap between the stacked chips is then encapsulated with an epoxy underfill resin having a low coefficient of thermal expansion (CTE) that is filled with hyperfine filler particles to reduce the thermal stress of the micro bumps. Using these techniques, the micro bumps can have a pitch of about 20 microns and the interchip wiring length can be short. However, the chips are stacked after dicing, rather than at the wafer level, and the thermocompression bonding process can require relatively high temperatures and bonding forces. See Tomita et al., “Advanced Packaging Technologies on 3D Stacked LSI utilizing the Micro Interconnections and the Layered Microthin Encapsulation,” Proc. 2001Electronic Components and Technology Conference (2001); Takahashi et al., “Development of Advanced 3D Chip Stacking Technology with Ultra-Fine Interconnections,” Proc. 2001 Electronic Components and Technology Conference (2001); and Umemoto et al., “Superfine Flip-Chip Interconnection in 20 μm-Pitch Utilizing Reliable Microthin Underfill Technology for 3D Stacked LSI,” Proc. 2002Electronic Components and Technology Conference, 1454 (2002), which are incorporated herein by reference.
Recently, vertically integrated circuits have been fabricated at the wafer level using stacking of thinned wafers and vertical interchip wiring. Vertical electrical connections are formed between the uppermost metal layers of the bonded wafers by fabrication and metal refill of high aspect ratio interchip vias. However, this requires that the I/O pads of the adjoining stacked wafers be precisely located over each other to make the vertical electrical connections. Therefore, the bonding process requires a precise optically adjusted alignment process to carefully adjust the lithographic levels of the top and bottom wafers. Furthermore, the process uses polyimide as the intermediate glue layer. Polyimide requires a high temperature cure (i.e., about 380° C.), is hydrophilic (i.e., moisture absorption of about 2%), and is conformal, necessitating that the polyimide be coated on a relatively featureless bottom wafer surface. Finally, this process does not provide for the inclusion of additional interconnect circuitry and passives in the intermediate layer. See Ramm et al., “Three dimensional metallization for vertically integrated circuits,” Microelectronic Engineering 37/38, 39 (1997), which is incorporated herein by reference.
The microsystem-on-a-chip (μSOC) technology of the present invention addresses the need for heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The μSOC is a modular, multi-function, multi-chip stacked package that provides all of the needed system-level functions. A highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less. Furthermore, the μSOC package eliminates the use of wirebonds and solder joints, thus making the package inherently more robust for applications exposed to extreme mechanical shock and vibration environments. The μSOC package will enable wireless distributed sensor systems comprising miniaturized, unattended, unobtrusive, surveillance devices for monitoring for military battlefields, infrastructure systems, and manufacturing processes.